#ifndef PERIPHIAL_DRVS_TIMER_PWM_H
#define PERIPHIAL_DRVS_TIMER_PWM_H

#define MMR_TIMER0_MUX_SRC   (0x4508060u)
#define MMR_TIMER_MUX_HFOSC0 (0x0u)
#define TIMER0_BASE_ADDR     (0x04800000u)
#define TIMER2_INT_NUM       (22u)

#define TIMER_TIOCP_CFG_OFFSET          (0x10u)
#define TIMER_TIOCP_CFG_RESET_SHIFT     (0)
#define TIMER_TIOCP_CFG_IDLE_MODE_SHIFT (2)
#define TIMER_TIOCP_CFG_IDLE_MODE_MASK  (0x3u << TIMER_TIOCP_CFG_IDLE_MODE_SHIFT)
#define TIMER_TIOCP_CFG_IDLE_MODE_SMART (0x2u)

#define TIMER_IRQSTATUS_OFFSET        (0x28u)
#define TIMER_IRQSTATUS_MATCH_FLAG    (0x1u)
#define TIMER_IRQSTATUS_OVERFLOW_FLAG (0x2u)
#define TIMER_IRQSTATUS_SET_OFFSET    (0x2Cu)

#define TIMER_TCLR_OFFSET                 (0x38u)
#define TIMER_TCLR_START_SHIFT            (0)
#define TIMER_TCLR_START_MASK             (0x1u << TIMER_TCLR_START_SHIFT)
#define TIMER_TCLR_AUTO_RELOAD_SHIFT      (1)
#define TIMER_TCLR_AUTO_RELOAD_MASK       (0x1u << TIMER_TCLR_AUTO_RELOAD_SHIFT)
#define TIMER_TCLR_PTV_SHIFT              (2)
#define TIMER_TCLR_PTV_MASK               (0x7u << TIMER_TCLR_PTV_SHIFT)
#define TIMER_TCLR_PRESCALER_ENABLE_SHIFT (5)
#define TIMER_TCLR_PRESCALER_ENABLE_MASK  (0x1u << TIMER_TCLR_PRESCALER_ENABLE_SHIFT)
#define TIMER_TCLR_CE_SHIFT               (6)
#define TIMER_TCLR_CE_MASK                (0x1u << TIMER_TCLR_CE_SHIFT)
#define TIMER_TCLR_SCPWM_SHIFT            (7)
#define TIMER_TCLR_SCPWM_MASK             (0x1u << TIMER_TCLR_SCPWM_SHIFT)
#define TIMER_TCLR_TRG_SHIFT              (10)
#define TIMER_TCLR_TRG_MASK               (0x3 << TIMER_TCLR_TRG_SHIFT)
#define TIMER_TCLR_TRG_OVERFLOW_ONLY      (0x1u << TIMER_TCLR_TRG_SHIFT)
#define TIMER_TCLR_TRG_OVERFLOW_AND_MATCH (0x2u << TIMER_TCLR_TRG_SHIFT)
#define TIMER_TCLR_PT_SHIFT               (12)
#define TIMER_TCLR_PT_MASK                (0x1u << TIMER_TCLR_PT_SHIFT)
#define TIMER_TCLR_PT_PULSE               (0x0u << TIMER_TCLR_PT_SHIFT)
#define TIMER_TCLR_PT_TOGGLE              (0x1u << TIMER_TCLR_PT_SHIFT)
#define TIMER_TCLR_GPO_CFG_SHIFT          (14)
#define TIMER_TCLR_GPO_CFG_MASK           (0x1u << TIMER_TCLR_GPO_CFG_SHIFT)
#define TIMER_TCLR_GPO_CFG_PWM            (0x0u << TIMER_TCLR_GPO_CFG_SHIFT)
#define TIMER_TCLR_GPO_CFG_TRIGGER        (0x1u << TIMER_TCLR_GPO_CFG_SHIFT)

#define TIMER_TCRR_OFFSET (0x3cu)
#define TIMER_TLDR_OFFSET (0x40u)
#define TIMER_TTGR_OFFSET (0x44u)
#define TIMER_TMAR_OFFSET (0x4cu)

#endif // PERIPHIAL_DRVS_TIMER_PWM_H
